With the advance of technology, the size (e.g. lateral extent) of chips (or dies) has decreased. Whilst the size (e.g. lateral extent) of a chip may have decreased, the number of interconnects that may, for example, couple (e.g. electrically couple) the chip to a circuit board (e.g. a printed circuit board) has remained stable, and in some examples, has increased. Accordingly, a distance between adjacent interconnects, which may also be referred to as a pitch of the interconnects, has decreased.
The plurality of interconnects that may, for example, couple (e.g. electrically couple) the chip to a circuit board (e.g. a printed circuit board) may be coupled to a plurality of pads that may be provided at a surface of the chip (or die). Consequently, a pitch of the plurality of pads of the chip (or die) has decreased as well. The decrease in the pitch of the plurality of pads of the chip may pose a challenge in packaging the chip (or die). New packaging solutions may be needed.